1. Field of the Invention
The present invention relates to a synchronization circuit, in particularly a synchronization circuit in an asynchronous transfer mode (ATM) communication system for synchronization of ATM cells connected on the lines in the system, that is, cell synchronization.
2. Description of the Related Art
At the present time, the Consultative Committee for International Telegraph and Telephone (CCITT) is proposing ATM communications suitable for broadband Integrated Services Digital Networks (ISDNs) etc., that is, data transfer by an asynchronous transfer mode, and is pressing forward with standardization of such systems. One proposal is for use of a full ATM for a layer.
If full ATM is used for a layer in accordance with that CCITT proposal, technology would become necessary for extracting each and every ATM cell which are units of data transfer by the ATM communications network. That is, it would be necessary to establish cell synchronization and detect the positions of the cells.
To extract cells in this way, cyclic redundancy check (CRC) arithmetic operations are said to be extremely effective. That is, a CRC arithmetic operation is performed on the header of a cell, the cells are detected when the results of the CRC arithmetic operation becomes fixed values, and cell synchronization is performed. In this case, even detection of errors of the cell header itself can naturally be performed by the inherent CRC function. Note that even when an error is included in a cell, cell synchronization can be sufficiently ensured by so-called front protection and rear protection.
Usually, ATM cells include the header and a payload for transmitting information. The header includes a field known as a header error control (HEC). The result of the CRC arithmetic operation are written into this HEC. The present invention relates to a synchronization circuit which writes, at the transmission side of the ATM cell, the result of the CRC arithmetic operation on the header in the HEC as a cell synchronization establishment signal and detects, at the reception side of the ATM cell, the coincidence of the results of the CRC arithmetic operation on the header of the received ATM cell and the result of the CRC arithmetic operation written at the transmission side in the HEC of the ATM cell so as to detect if cell synchronization has been achieved and to output a synchronization detection signal.
A detailed explanation will be made later of several conventional CRC arithmetic units referring to the attached figures. However, conventional CRC arithmetic units basically are constructed to receive input bits trains having definite time series, to perform CRC arithmetic operations on the bit trains, and to obtain a CRC arithmetic operation result.
On the other hand, in the ATM transmission art, a synchronization circuit of the full ATM transmission system does not cover such input bit trains having definite time series, but cover input bit trains having indefinite time series (ATM cell groups), so it is necessary to shift the input bit trains one bit at a time to continuously obtain CRC arithmetic operations results C.sub.out.
If the conventional CRC arithmetic unit is assembled and designed to perform a CRC arithmetic operation on such input bit trains having indefinite time series (ATM cell groups), the assembled CRC arithmetic operation circuit would enlarge the size of the apparatus (hardware). Further, if the CRC arithmetic operation is performed on ultrahigh speed data, the problem will arise of an increased processing delay.